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chengpin CP8053 eprom/rom-based 8-bit microcontroller series p.1/CP8053 devices included in this data sheet: ? CP8053e : eprom device ? CP8053 : mask rom device features ? only 42 single word instructions ? all instructions are single cycle except for program branches which are two-cycle ? 13-bit wide instructions ? all rom/eprom area goto instruction ? all rom/eprom area subroutine call instruction ? 8-bit wide data path ? 5-level deep hardware stack ? operating speed: dc-20 mhz clock input dc-100 ns instruction cycle device pins # i/o # eprom/rom (byte) ram (byte) CP8053/53e 14 12 1k 49 ? direct, indirect addressing modes for data accessing ? 8-bit real time clock/co unter (timer0) with 8-bit programmable prescaler ? internal power-on reset (por) ? built-in low voltage detector (lvd) for brown-out reset (bor) ? power-up reset timer (pwrt) and oscillator start-up timer(ost) ? on chip watchdog timer (wdt) with internal oscillator for reliable operation and soft-ware watch-dog enable/disable control ? two i/o ports ioa and iob with i ndependent dire ction control ? soft-ware i/o pull-high/pull- down or open-drain control ? one internal interrupt source: timer0 overflow; two ex ternal interrupt source: int pin, port b input change ? wake-up from sleep by int pin or port b input change ? power saving sleep mode ? built-in 8mhz, 4mhz, 1mhz, and 455khz internal rc oscillator ? programmable code protection ? built-in internal rc oscillator ? selectable oscillator options: - erc: external resistor/capacitor oscillator - irc: internal or external resi stor/internal capacitor oscillator - hf: high frequency crystal/resonator oscillator - lf: low frequency crystal oscillator ? wide-operating voltage range: - eprom : 2.3v to 5.5v - rom : 2.3v to 5.5v
chengpin CP8053 p.2/CP8053 general description the CP8053 series is a family of low-cost, high speed, high noise immunity, eprom/rom-based 8-bit cmos microcontrollers. it employs a risc architecture with only 42 instructions. all instructions are single cycle except for program branches which take two cycles. the easy to use and easy to remember instruction set reduces development time significantly. the CP8053 series consists of power-on reset (por), brown-out reset (bor), power-up reset timer (pwrt), oscillator start-up timer(ost), watchdog timer, eprom/rom, sram, tri-state i/o port, i/o pull-high/open-drain/pull-down control, power saving sl eep mode, real time programmable clock/counter, interrupt, wake-up from sleep mode, and code protec tion for eprom products. there are four oscillator configurations to choose from, includin g the power-saving lp (low power) osc illator and cost saving rc oscillator. the CP8053 address 1k13 of program memory. the CP8053 can directly or ind irectly address its register files and data memory. all special function reg isters including the program counter are mapped in the data memory. block diagram alu watchdog timer oscillator circuit timer0 porta portb program counter 5-level stack eprom / rom sram instruction decoder accumulator fsr interrupt control
chengpin CP8053 p.3/CP8053 pin connection pdip, sop pin descriptions name i/o description ioa0 ~ ioa3 i/o ioa0 ~ ioa3 as bi-direction i/o pin software controlled pull-down iob0/int i/o bi-direction i/o pin with system wake-up function software controlled pull-high/open-drain/pull-down / external interrupt input iob1 i/o bi-direction i/o pin with system wake-up function software controlled pull-high/open-drain/pull-down iob2/t0cki i/o bi-direction i/o pin with system wake-up function software controlled pull-high/open-drain/pull-down / external clock input to timer0 iob3/rstb i iob3 is input pin only with system wake-up function / system clear (reset) input. active low reset to the device. weak pull-high always on if configured as rstb. iob4/osco i/o bi-direction i/o pin with system wake-up fu nction (rcout optional in irc, erc mode) software controlled pull-high/open-drain / oscillator crystal output (xt, lp mode) outputs with the instruction cycle ra te (rcout optional in irc,erc mode) iob5/osci i/o bi-direction i/o pin with system wake-up function (irc mode) software controlled pull-high/open-drain / oscillator crystal input (xt, lp mode) external clock source input (erc mode) iob6 ~ iob7 i/o bi-direction i/o pin with system wake-up function software controlled pull-high/open-drain vdd - positive supply vss - ground legend: i=input, o=output, i/o=input/output CP8053/53e ioa0 iob7 iob6 vdd iob5/osci iob4/osco iob3/rstb ioa2 ioa3 ioa1 vss iob1 iob2/t0cki iob0/int 14 1 13 12 11 10 9 8 2 3 4 5 6 7
chengpin cp 8053 p.4/CP8053 1.0 memory organization CP8053 memory is organi zed into program memory and data memory. 1.1 program memory organization the CP8053 have a 10-bit program counter capabl e of addressing a 1k13 program memory space. the reset vector for the CP8053 is at 3ffh. the h/w interrupt vector is at 008h. a nd the s/w interrupt ve ctor is at 002h. CP8053 supports all rom/eprom area call/goto instructions without page. figure 1.1: program memory map and stack pc<9:0> stack 1 stack 2 stack 3 stack 4 stack 5 3ffh reset vector : : 008h h/w interrupt vector 002h s/w interrupt vector 000h CP8053/53e
chengpin CP8053 p.5/CP8053 1.2 data memory organization data memory is composed of special functi on registers and general purpose registers. the general purpose registers are accessed either di rectly or indirectly through the fsr register. the special function registers are registers used by the cpu and peripheral functions to control the operation of the device. table 1.1: registers file map for CP8053 series address description 00h indf 01h tmr0 02h pcl n/a option 03h status 04h fsr 05h porta 05h iosta 06h portb 06h iostb 07h general purpose register 08h pcon 09h wucon 0ah pchbuf 0bh pdcon 0ch odcon 0dh phcon 0eh inten 0fh intflag 10h ~ 3fh general purpose registers table 1.2: the registers controlled by option or iost instructions address name b7 b6 b5 b4 b3 b2 b1 b0 n/a (w) option * intedg t0cs t0se psa ps2 ps1 ps0 05h (w) iosta port a i/o control register 06h (w) iostb port b i/o control register table 1.3: operational registers map address name b7 b6 b5 b4 b3 b2 b1 b0 00h (r/w) indf uses contents of fsr to addr ess data memory (not a physical register) 01h (r/w) tmr0 8-bit real-time clock/counter 02h (r/w) pcl low order 8 bits of pc 03h (r/w) status rst gp1 gp0 to pd z dc c 04h (r/w) fsr * * indirect data memory address pointer 05h (r/w) porta ioa3 ioa2 ioa1 ioa0 06h (r/w) portb iob7 iob6 iob5 iob4 iob3 iob2 iob1 iob0 07h (r/w) sram general purpose register 08h (r/w) pcon wdte eis lvdte * * * * * 09h (r/w) wucon wub7 wub6 wub5 wub4 wub3 wub2 wub1 wub0 0ah (r/w) pchbuf - - - - - - 2 msbs buffer of pc 0bh (r/w) pdcon /pdb2 /pdb1 /pdb0 /pda3 /pda2 /pda1 /pda0 0ch (r/w) odcon odb7 odb6 od b5 odb4 odb2 odb1 odb0 0dh (r/w) phcon /phb7 /phb6 /phb5 /phb4 /phb2 /phb1 /phb0 0eh (r/w) inten gie * * * * intie pbie t0ie 0fh (r/w) intflag - - - - - intif pbif t0if legend: - = unimplemented, read as ?0?, * = unimplemented, read as ?1?,
chengpin CP8053 p.6/CP8053 2.0 functional descriptions 2.1 operational registers 2.1.1 indf (indirect addressing register) address name b7 b6 b5 b4 b3 b2 b1 b0 00h (r/w) indf uses contents of fsr to addr ess data memory (not a physical register) the indf register is not a physical register. any instru ction accessing the indf register can actually access the register pointed by fsr register. reading the indf register itself indirectly (fsr=?0?) will read 00h. writing to the indf register indirectly results in a no-oper ation (although status bits may be affected). the bits 5-0 of fsr register are used to se lect up to 64 registers (address: 00h ~ 3fh). example 2.1: indirect addressing ?3 register file 38 contains the value 10h ?3 register file 39 contains the value 0ah ?3 load the value 38 into the fsr register ?3 a read of the indf register will return the value of 10h ?3 increment the value of the fs r register by one (@fsr=39h) ?3 a read of the indr register now w ill return the value of 0ah. figure 2.1: direct/indirect addressing direct addressing indirect addressing 5 from opcode 0 5 from fsr register 0 location select 00h location select addressing indf register 3fh
chengpin CP8053 p.7/CP8053 2.1.2 tmr0 (time clock/counter register) address name b7 b6 b5 b4 b3 b2 b1 b0 01h (r/w) tmr0 8-bit real-time clock/counter the timer0 is a 8-bit timer/counter. the clock source of ti mer0 can come from the instruction cycle clock or by an external clock source (t0cki pin) defined by t0cs bi t (option<5>). if t0cki pin is selected, the timer0 is increased by t0cki signal rising/falling edge (selected by t0se bit (option<4>)). the prescaler is assigned to timer0 by clearing the psa bi t (option<3>). in this case, the prescaler will be cleared when tmr0 register is written with a value. 2.1.3 pcl (low bytes of program counter) & stack address name b7 b6 b5 b4 b3 b2 b1 b0 02h (r/w) pcl low order 8 bits of pc CP8053 devices have a 10-b it wide program counter (pc) and five-level deep 10-bit hardware push/pop stack. the low byte of pc is called the pcl register. this register is readable and writable. the high byte of pc is called the pch register. this register contains the pc<9:8> bits and is not directly readable or writable. all updates to the pch register go through the pchbuf register. as a program in struction is executed, the program counter will contain the address of the next program instru ction to be executed. the pc value is increased by one, every instruction cycle, unless an instruction changes the pc. for a goto instruction, the pc<9:0> is provided by the goto instruction word. the pcl register is mapped to pc<7:0>, and the pchbuf r egister is not updated. for a call instruction, the pc<9:0> is provided by the call instruction word. the next pc will be loaded (pushed) onto the top of stack. the pcl regi ster is mapped to pc<7:0>, and the pchbuf register is not updated. for a retia, retfie, or return instruction, the pc are updated (poped) from t he top of stack. the pcl register is mapped to pc<7:0>, and t he pchbuf register is not updated. for any instruction where the pcl is t he destination, the pc<7:0> is provided by the instruction word. however, the pc<9:8> will come from the pchbuf<1:0> register (pchbuf ? pch). pchbuf register is never updat ed with the contents of pch.
chengpin cp 8053 p.8/CP8053 figure 2.2: loading of pc in different situations situation 1: goto instruction pch pcl 9 8 7 0 pc - - - - - - pchbuf situation 2: call instruction pch pcl 9 8 7 0 pc - - - - - - pchbuf situation 3: retia, retfi e, or return instruction pch pcl 9 8 7 0 pc - - - - - - pchbuf situation 4: instruction with pcl as destination pch pcl 9 8 7 0 pc - - - - - - pchbuf note: 1. pchbuf is used only for instruct ion with pcl as destination for CP8053. opcode<9:0> pchbuf<1:0> alu result<7:0> or opcode<7:0> stack<9:0> stack<9:0> opcode<9:0>
chengpin CP8053 p.9/CP8053 2.1.4 status (status register) address name b7 b6 b5 b4 b3 b2 b1 b0 03h (r/w) status rst gp1 gp0 to pd z dc c this register contains t he arithmetic status of t he alu, the reset status. if the status register is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is disabled. these bits are set or clear ed according to the device logic. furthermore, the to and pd bits are not writable. therefore, the result of an instruction with the status r egister as destination may be different than intended. for example, clrr status will clear the upper three bits and set the z bit. this leaves the status register as 000u u1uu (where u = unchanged). c : carry/borrow bit. addar, addia = 1, a carry occurred. = 0, a carry did not occur. subar, subia = 1, a borrow did not occur. = 0, a borrow occurred. note : a subtraction is executed by adding the two?s complement of the second operand. for rotate (rrr, rlr) instructions, this bit is loaded with either the high or low order bit of the source register. dc : half carry/half borrow bit. addar, addia = 1, a carry from the 4th low order bit of the result occurred. = 0, a carry from the 4th low order bit of the result did not occur. subar, subia = 1, a borrow from the 4th low order bit of the result did not occur. = 0, a borrow from the 4th low order bit of the result occurred. z : zero bit. = 1, the result of a logic operation is zero. = 0, the result of a logic operation is not zero. pd : power down flag bit. = 1, after power-up or by the clrwdt instruction. = 0, by the sleep instruction. to : time overflow flag bit. = 1, after power-up or by the clrwdt or sleep instruction. = 0, a watch-dog time overflow occurred. gp1:gp0 : general purpose read/write bits. rst : bit for wake-up type. = 1, wake-up from sleep on port b input change. = 0, wake-up from other reset types.
chengpin CP8053 p.10/CP8053 2.1.5 fsr (indirect data memory address pointer) address name b7 b6 b5 b4 b3 b2 b1 b0 04h (r/w) fsr * * indirect data memory address pointer bit5:bit0 : select registers address in the indirect addressing mode. see 2.1.1 for detail description. bit7:bit6 : not used. read as ?1?s. 2.1.6 porta, portb (port data registers) address name b7 b6 b5 b4 b3 b2 b1 b0 05h (r/w) porta ioa3 ioa2 ioa1 ioa0 06h (r/w) portb iob7 iob6 iob5 iob4 iob3 iob2 iob1 iob0 reading the port (porta, portb register) reads the status of the pins independent of the pin?s input/output modes. writing to these ports will wr ite to the port data latch. porta is a 4-bit port data register. only the low order 4 bits are used (porta<3:0>). bits 7-4 are general purpose read/write bits. portb is a 8-bit port data register. and iob3 is input only. 2.1.7 pcon (power control register) address name b7 b6 b5 b4 b3 b2 b1 b0 08h (r/w) pcon wdte eis lvdte * * * * * bit4:bit0 : not used. read as ?1?s. lvdte : lvdt (low voltage detector) enable bit. = 0, disable lvdt. = 1, enable lvdt. eis : define the function of iob0/int pin. = 0, iob0 (bi-directional i/o pin) is selected. the path of int is masked. = 1, int (external interrupt pin) is selected. in this case , the i/o control bit of iob0 must be set to ?1?. the path of port b input change of iob0 pin is masked by hard ware, the status of int pi n can also be read by way of reading portb. wdte : wdt (watch-dog timer) enable bit. = 0, disable wdt. = 1, enable wdt. 2.1.8 wucon (port b input change interrupt/wake-up control register) address name b7 b6 b5 b4 b3 b2 b1 b0 09h (r/w) wucon wub7 wub6 wub5 wub4 wub3 wub2 wub1 wub0 wub0 : = 0, disable the input change inte rrupt/wake-up function of iob0 pin. = 1, enable the input change interr upt/wake-up function of iob0 pin. wub1 : = 0, disable the input change inte rrupt/wake-up function of iob1 pin. = 1, enable the input change interr upt/wake-up function of iob1 pin. wub2 : = 0, disable the input change inte rrupt/wake-up function of iob2 pin.
chengpin cp 8053 p.11/CP8053 = 1, enable the input change interr upt/wake-up function of iob2 pin. wub3 : = 0, disable the input change inte rrupt/wake-up function of iob3 pin. = 1, enable the input change interr upt/wake-up function of iob3 pin. wub4 : = 0, disable the input change inte rrupt/wake-up function of iob4 pin. = 1, enable the input change interr upt/wake-up function of iob4 pin. wub5 : = 0, disable the input change inte rrupt/wake-up function of iob5 pin. = 1, enable the input change interr upt/wake-up function of iob5 pin. wub6 : = 0, disable the input change inte rrupt/wake-up function of iob6 pin. = 1, enable the input change interr upt/wake-up function of iob6 pin. wub7 : = 0, disable enable the input change interrupt/wake-up function of iob7 pin. = 1, enable the input change interr upt/wake-up function of iob7 pin. 2.1.9 pchbuf (high byte buffer of program counter) address name b7 b6 b5 b4 b3 b2 b1 b0 0ah (r/w) pchbuf - - - - - - 2 msbs buffer of pc bit1:bit0 : see 2.1.3 for detail description. bit7:bit2 : not used. read as ?0?s. 2.1.10 pdcon (pull-down control register) address name b7 b6 b5 b4 b3 b2 b1 b0 0bh (r/w) pdcon /pdb2 /pdb1 /pdb0 /pda3 /pda2 /pda1 /pda0 /pda0 : = 0, enable the internal pull-down of ioa0 pin. = 1, disable the internal pull-down of ioa0 pin. /pda1 : = 0, enable the internal pull-down of ioa1 pin. = 1, disable the internal pull-down of ioa1 pin. /pda2 : = 0, enable the internal pull-down of ioa2 pin. = 1, disable the internal pull-down of ioa2 pin. /pda3 : = 0, enable the internal pull-down of ioa3 pin. = 1, disable the internal pull-down of ioa3 pin. /pdb0 : = 0, enable the internal pull-down of iob0 pin. = 1, disable the internal pull-down of iob0 pin. /pdb1 : = 0, enable the internal pull-down of iob1 pin. = 1, disable the internal pull-down of iob1 pin. /pdb2 : = 0, enable the internal pull-down of iob2 pin. = 1, disable the internal pull-down of iob2 pin. bit7 : general purpose read/write bit.
chengpin CP8053 p.12/CP8053 2.1.11 odcon (open-drain control register) address name b7 b6 b5 b4 b3 b2 b1 b0 0ch (r/w) odcon odb7 odb6 od b5 odb4 odb2 odb1 odb0 odb0 : = 0, disable the internal open-drain of iob0 pin. = 1, enable the internal open-drain of iob0 pin. odb1 : = 0, disable the internal open-drain of iob1 pin. = 1, enable the internal open-drain of iob1 pin. odb2 : = 0, disable the internal open-drain of iob2 pin. = 1, enable the internal open-drain of iob2 pin. bit3 : general purpose read/write bit. odb4 : = 0, disable the internal open-drain of iob4 pin. = 1, enable the internal open-drain of iob4 pin. odb5 : = 0, disable the internal open-drain of iob5 pin. = 1, enable the internal open-drain of iob5 pin. odb6 : = 0, disable the internal open-drain of iob6 pin. = 1, enable the internal open-drain of iob6 pin. odb7 : = 0, disable the internal open-drain of iob7 pin. = 1, enable the internal open-drain of iob7 pin. 2.1.12 phcon (pull-high control register) address name b7 b6 b5 b4 b3 b2 b1 b0 0dh (r/w) phcon /phb7 /phb6 /phb5 /phb4 /phb2 /phb1 /phb0 /phb0 : = 0, enable the internal pull-high of iob0 pin. = 1, disable the internal pull-high of iob0 pin. /phb1 : = 0, enable the internal pull-high of iob1 pin. = 1, disable the internal pull-high of iob1 pin. /phb2 : = 0, enable the internal pull-high of iob2 pin. = 1, disable the internal pull-high of iob2 pin. bit3 : general purpose read/write bit. /phb4 : = 0, enable the internal pull-high of iob4 pin. = 1, disable the internal pull-high of iob4 pin. /phb5 : = 0, enable the internal pull-high of iob5 pin. = 1, disable the internal pull-high of iob5 pin. /phb6 : = 0, enable the internal pull-high of iob6 pin. = 1, disable the internal pull-high of iob6 pin. /phb7 : = 0, enable the internal pull-high of iob7 pin. = 1, disable the internal pull-high of iob7 pin.
chengpin cp 8053 p.13/CP8053 2.1.13 inten (interrupt mask register) address name b7 b6 b5 b4 b3 b2 b1 b0 0eh (r/w) inten gie * * * * intie pbie t0ie t0ie : timer0 overflow interrupt enable bit. = 0, disable the timer0 overflow interrupt. = 1, enable the timer0 overflow interrupt. pbie : port b input change interrupt enable bit. = 0, disable the port b input change interrupt. = 1, enable the port b input change interrupt . intie : external int pin interrupt enable bit. = 0, disable the external int pin interrupt. = 1, enable the external int pin interrupt. bit6:bit3 : not used. read as ?1?s. gie : global interrupt enable bit. = 0, disable all interrupts. for wake-up from sleep mode through an interrupt event, the device will continue execution at the instruction after the sleep instruction. = 1, enable all un-masked interrupts. for wake-up from sleep mode through an interrupt event, the device will branch to the interrupt address (008h). note : when an interrupt event occur with the gie bit and its corresponding interrupt enable bit are all set, the gie bit will be cleared by hardware to disable any further interrupts. the retfie instruction will exit the interrupt routine and set the gie bit to re-enable interrupt. 2.1.14 intflag (interrupt status register) address name b7 b6 b5 b4 b3 b2 b1 b0 0fh (r/w) intflag - - - - - intif pbif t0if t0if : timer0 overflow interrupt flag. set wh en timer0 overflows, reset by software. pbif : port b input change interrupt flag. set wh en port b input changes, reset by software. intif : external int pin interrupt flag. set by rising/falling (selected by intedg bit (option<6>)) edge on int pin, reset by software. bit7:bit3 : not used. read as ?0?s. 2.1.15 acc (accumulator) address name b7 b6 b5 b4 b3 b2 b1 b0 n/a (r/w) acc accumulator accumulator is an internal data transfer, or inst ruction operand holding. it can not be addressed.
chengpin CP8053 p.14/CP8053 2.1.16 option register address name b7 b6 b5 b4 b3 b2 b1 b0 n/a (w) option * intedg t0cs t0se psa ps2 ps1 ps0 by executing the option instruction, the contents of t he acc register will be transferred to the option register. the option register is a 7-bit wide, write-only register which contains various control bits to configure the timer0/wdt prescaler, timer0, and the external int interrupt. the option register are ?write-only? and are set all ?1?s except intedg bit. ps2:ps0 : prescaler rate select bits. ps2:ps0 timer0 rate wdt rate 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 psa : prescaler assign bit. = 1, wdt (watch-dog timer). = 0, tmr0 (timer0). t0se : tmr0 source edge select bit. = 1, falling edge on t0cki pin. = 0, rising edge on t0cki pin. t0cs : tmr0 clock source select bit. = 1, external t0cki pin. pin iob2/t0cki is forced to be an input even if iost iob2 = ?0?. = 0, internal instruction clock cycle. intedg : interrupt edge select bit. = 1, interrupt on rising edge of int pin. = 0, interrupt on falling edge of int pin. bit7 : not used. 2.1.17 iosta & iostb (port i/o control registers) address name b7 b6 b5 b4 b3 b2 b1 b0 n/a (w) iosta port a i/o control register n/a (w) iostb port b i/o control register the port i/o control registers are loa ded with the contents of the acc regist er by executing the iost r (05h~06h) instruction. a ?1? from a iost register bit puts the corres ponding output driver in hi-impedance state (input mode). a ?0? enables the output buffer and puts the contents of the output data latch on the selected pins (output mode). the iost registers are ?write-only? and ar e set (output drivers disabled) upon reset.
chengpin CP8053 p.15/CP8053 2.2 i/o ports port a and port b are bi-directional tri-st ate i/o ports. port a is a 4-pin i/o port. port b is a 8-pin i/o port. please note that iob3 is an input only pin. all i/o pins have data direction control registers (iosta, ios tb) which can config ure these pins as output or input. the exceptions are iob3 which is input only and iob2 wh ich may be controlled by the t0cs bit (option<5>). iob<7:4> and iob<2:0> have its corresponding pull-high contro l bits (phcon register) to enable the weak internal pull-high. the weak pull-high is automatically turn ed off when the pin is conf igured as an output pin. ioa<3:0> and iob<2:0> have its corresponding pull-down control bits (pdcon register) to enable the weak internal pull-down. the weak pull-down is automatically turned off when the pin is conf igured as an output pin. iob<7:4> and iob<2:0> have its corresponding open-drain c ontrol bits (odcon register) to enable the open-drain output when these pins are configured to be an output pin. iob<7:0> also provides the input change interrupt/wake- up function. each pin has its corresponding input change interrupt/wake-up enable bits (wucon) to sele ct the input change interrupt/wake-up source. the iob0 is also an external interrupt input signal by se tting the eis bit (pcon<6>). in this case, iob0 input change interrupt/wake-up function will be disabled by hardware even if it is enabled by software. the configuration words can set several i/os to altern ate functions. when acting as alternate functions the pins will read as ?0? during port read. figure 2.3: block diagram of i/o pins ioa3 ~ ioa0 : pull-down is not shown in the figure iob3 : d q iost latch > en q i/o pin d q data latch > en q d a t a b us iost r wr port rd port i/o pin rd port q d latch q en< set pbif wubn data bus
chengpin cp 8053 p.16/CP8053 iob0/int : pull-high/pull-down and open-drain are not shown in the figure iob7 ~ iob1 : pull-high/pull-down and open-drain are not shown in the figure d q iost latch > en q i/o pin d q data latch > en q d a t a b us iost r wr port rd port q d latch q en< set pbif wubn eis eis int intedg d q iost latch > en q i/o pin d q data latch > en q d a t a b us iost r wr port rd port q d latch q en< set pbif wubn
chengpin CP8053 p.17/CP8053 2.3 timer0/wdt & prescler 2.3.1 timer0 the timer0 is a 8-bit timer/counter. the clock source of time r0 can come from the internal clock or by an external clock source (t0cki pin). 2.3.1.1 using timer0 with an internal clock : timer mode timer mode is selected by clearing the t0cs bit (option< 5>). in timer mode, the timer0 register (tmr0) will increment every instruction cycle (without prescaler). if tmr0 register is written, the in crement is inhibited for the following two cycles. 2.3.1.2 using timer0 with an external clock : counter mode counter mode is selected by setting the t0cs bit (opton<5>) . in this mode, timer0 will increment either on every rising or falling edge of pin t0ckl. the incrementing edge is determined by the source edge select the rising edge. the external clock requirement is due to internal phase cloc k (tosc) synchronization. also, there is a delay in the actual incrementing of timer0 after synchronization. when no prescaler is used, the external clock input is the same as the prescaler output. the synchronization of t0cki with the internal phase clocks is accomplished by sa mpling the prescaler output on the t2 and t4 cycles of the internal phase clocks. therefore, it is necessary for t0cki to be high for at least 2 t osc and low for at least 2 tosc. when a prescaler is used, the external clock input is divid ed by the asynchronous prescaler. for the external clock to meet the sampling requirement, the ripple counter must be taken into account. therefore, it is necessary for t0cki to have a period of at least 4tosc divided by the prescaler value. 2.3.2 watchdog timer (wdt) the watchdog timer (wdt) is a free running on-chip rc oscilla tor which does not require any external components. so the wdt will still run even if the cl ock on the osci and osco pins is turned off, such as in sleep mode. during normal operation or in sleep mode, a wdt time -out will cause the device reset and the to bit (status<4>) will be cleared. the wdt can be disabled by clearing the control bit wdte (pcon<7>) to ?0?. the wdt has a nominal time-out period of 18 ms, 4. 5ms, 288ms or 72ms selected by sut<1:0> bits of configuration word (without prescaler). if a longer time-out period is desired, a prescaler with a division ratio of up to 1:128 can be assigned to the wdt controlled by the opti on register. thus, the longest time-out period is approxmately 36.8 seconds. the clrwdt instruction clears the wdt and the prescaler, if assigned to the wdt, and prevents it from timing out and generating a device reset. the sleep instruction resets the wdt and the prescaler, if assigned to the wdt. this gives the maximum sleep time before a wdt wake-up reset. 2.3.3 prescaler an 8-bit counter (down counter) is available as a prescale r for the timer0, or as a postscaler for the watchdog timer (wdt). note that the prescaler may be used by either the timer0 module or the wdt, but not both. thus, a prescaler assignment for the timer0 means that t here is no prescaler for the wdt, and vice-versa. the psa bit (option<3>) determines prescaler assi gnment. the ps<2:0> bits (option<2:0>) determine prescaler ratio. when the prescaler is assigned to the timer0 module, all in structions writing to the tm r0 register will clear the prescaler. when it is assigned to wdt, a clrwdt in struction will clear the prescaler along with the wdt. the prescaler is neither readable nor writable. on a reset, the prescaler contains all ?1?s. to avoid an unintended device reset, clrwdt or clrr tm r0 instructions must be executed when changing the prescaler assignment from timer0 to the wdt, and vice-versa.
chengpin CP8053 p.18/CP8053 figure 2.4: block diagram of the timer0/wdt prescaler 2.4 interrupts the CP8053 series has up to three sources of interrupt: 1. external interrupt int pin. 2. tmr0 overflow interrupt. 3. port b input change interrupt (pins iob7:iob0). intflag is the interrupt flag register that recodes the interrupt requests in the relative flags. a global interrupt enable bit, gie (inten<7>), enables (if set) all un-masked interrupts or disables (if cleared) all interrupts. individual interrupts can be enabled/disabled th rough their corresponding enable bits in inten register regardless of the status of the gie bit. when an interrupt event occur with the gie bit and its corres ponding interrupt enable bit are all set, the gie bit will be cleared by hardware to disable any further interrupts, and the next instruction wi ll be fetched from address 008h. the interrupt flag bits must be cleared by software be fore re-enabling gie bit to avoid recursive interrupts. the retfie instruction exits the interrupt rout ine and set the gie bit to re-enable interrupt. the flag bit (except pbif bit) in intflag register is set by interrupt event regardless of the status of its mask bit. reading the intflag register will be the logic and of intflag and inten. when an interrupt is generated by the int instruction, the next instruction will be fetched from address 002h. 2.4.1 external int interrupt external interrupt on int pin is rising or falli ng edge triggered selected by intedg (option<6>). when a valid edge appears on the int pin the flag bit intif (i ntflag<2>) is set. this interrupt can be disabled by clearing intie bit (inten<2>). the int pin interrupt can wake-up the system from sleep condition, if bit intie was set before going to sleep. if gie bit was set, the program will execute interrupt servic e routine after wake-up; or if gie bit was cleared, the program will execute next pc after wake-up. 2.4.2 timer0 interrupt an overflow (ffh ? 00h) in the tmr0 register will set the flag bit t0if (intflag<0>). this interrupt can be disabled by clearing t0ie bit (inten<0>). t0cki t0se t0cs mux 0 1 mux 0 1 watchdog timer psa 8-bit prescaler ps2:ps0 wdt time-out mux 1 0 psa mux 1 0 psa sync 2 cycles instruction cycle (fosc/4 or fosc/2 or fosc/8) tmr0 register data bus 8 set t0if flag on overflow
chengpin cp 8053 p.19/CP8053 2.4.3 port b input change interrupt an input change on iob<7:0> set flag bit pbif (intflag<1>). this interrupt can be disabled by clearing pbie bit (inten<1>). before the port b input change interrupt is enabled, readi ng portb (any instruction accessed to portb, including read/write instructions) is necessary. any pin which corresponding wubn bit (wucon<7:0>) is cleared to ?0? or configured as output or iob0 pin configured as int pin will be excluded from this function. the port b input change interrupt also can wake-up the sy stem from sleep condition, if bit pbie was set before going to sleep. and gie bit also decides whether or not the processor branches to the interrupt vector following wake-up. if gie bit was set, the program will execute interrupt service routine after wake-up; or if gie bit was cleared, the program will execute next pc after wake-up. 2.5 power-down mode (sleep) power-down mode is entered by executing a sleep instruction. when sleep instruction is executed, the pd bit (status<3>) is cleared, the to bit is set, the watchdog timer will be cleared and keeps running, and the oscillator driver is turned off. all i/o pins maintain the status they had before the sleep inst ruction was executed. 2.5.1 wake-up from sleep mode the device can wake-up from sleep mode through one of the following events: 1. rstb reset. 2. wdt time-out reset (if enabled). 3. interrupt from rb0/int pin, or portb change interrupt. external rstb reset and wdt time-out reset will cause a device reset. the pd and to bits can be used to determine the cause of device reset. the pd bit is set on power-up and is cleared when sleep instruction is executed. the to bit is cleared if a wdt time-out occurred. for the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set. wake-up is regardless of the gie bit. if gie bit is cleared, the devic e will continue execution at th e instruction after the sleep instruction. if the gie bit is set, the devic e will branch to the interrupt address (008h). in hf or lf oscillation mode, the system wake-up delay time is 18/4. 5/288/72ms (selected by sut<1:0> bits of configuration word ) plus 16 oscillator cycle time. and in irc or erc oscillation mode, the system wake-up delay time is 140us. 2.6 reset CP8053 devices may be res et in one of the following ways: 1. power-on reset (por) 2. brown-out reset (bor) 3. rstb pin reset 4. wdt time-out reset some registers are not affected in any reset conditi on. their status is unknown on power-on reset and unchanged in any other reset. most other registers are reset to a ?reset state? on power-on reset, rstb or wdt reset. a power-on reset pulse is gener ated on-chip when vdd rise is detected. to use this feature, the user merely ties the rstb pin to vdd. on-chip low voltage detector (lvd) places the device into reset when vdd is below a fixed voltage. this ensures that the device does not continue prog ram execution outside the valid operation vdd range. brown-out reset is typically used in ac line or heavy loads switched applications. a rstb or wdt wake-up from sleep also results in a device reset, and not a continuation of operation before sleep. the to and pd bits (status<4:3>) are set or cleared depending on the different reset conditions.
chengpin CP8053 p.20/CP8053 2.6.1 power-up reset timer(pwrt) the power-up reset timer provides a nominal 18/4.5/288/72m s (selected by sut<1:0> bits of configuration word ) (or 140us, varies based on oscillator selection and reset condition) delay after power-on reset (por), brown-out reset (bor), rstb reset or wdt time-out reset. the device is kept in reset state as long as the pwrt is active. the pwdt delay will vary from device to device due to vdd, temperature, and process variation. table 2.1: pwrt period oscillator mode power-on reset brown-out reset rstb reset wdt time-out reset erc & irc 18/4.5/ 288/72 ms 140 us hf & lf 18/4.5/288/72 ms 18/4.5/288/72ms 2.6.2 oscillator start-up timer(ost) the ost timer provides a 16 oscillator cycle delay (fro m osci input) after the pwrt delay (18/4.5/288/72ms) is over in hf or lf oscillation mode. th is delay ensures that the x?tal oscillator or resonator has started and stabilized. the device is kept in reset state as long as the ost is active. this counter only starts incrementing af ter the amplitude of the osci signal r eaches the oscillator input thresholds. 2.6.3 reset sequence when power-on reset (por), brown-out reset (bor), rstb reset or wdt time-out reset is detected, the reset sequence is as follows: 1. the reset latch is set and the pwrt & ost are cleared. 2. when the internal por, bor, rstb reset or wdt ti me-out reset pulse is finished, then the pwrt begins counting. 3. after the pwrt time-out, the ost is activated. 4. and after the ost delay is over, the reset latch will be cleared and thus end the on-chip reset signal. in hf or lf oscillation mode, the totally system reset del ay time is 18/4.5/288/72ms plus 16 oscillator cycle time. and in irc or erc oscillation mode, t he totally system reset delay time is 18/4.5/288/72ms after power-on reset (por), brown-out reset (bor), or 140us af ter rstb reset or wdt time-out reset. figure 2.5: simplified block di agram of on-chip reset circuit low voltage detector (lvd) vdd on-chip rc osc s q reset latch r q reset chip por reset power-up reset timer (pwrt) reset oscillator start-up timer (ost) wdt time-out wdt module osci power-on reset (por) bor rstb
chengpin cp 8053 p.21/CP8053 table 2.2: reset condi tions for all registers register address power-on reset brown-out reset rstb reset wdt reset acc n/a xxxx xxxx uuuu uuuu option n/a -011 1111 -011 1111 iosta n/a ---- 1111 ---- 1111 iostb n/a 1111 1111 1111 1111 indf 00h xxxx xxxx uuuu uuuu tmr0 01h xxxx xxxx uuuu uuuu pcl 02h 1111 1111 1111 1111 status 03h 0001 1xxx 000# #uuu fsr 04h 11xx xxxx 11uu uuuu porta 05h xxxx xxxx uuuu uuuu portb 06h xxxx xxxx uuuu uuuu general purpose register 07h xxxx xxxx uuuu uuuu pcon 08h 101- ---- 101- ---- wucon 09h 0000 0000 0000 0000 pchbuf 0ah ---- --00 ---- --00 pdcon 0bh 1111 1111 1111 1111 odcon 0ch 0000 0000 0000 0000 phcon 0dh 1111 1111 1111 1111 inten 0eh 0--- -000 0--- -000 intflag 0fh ---- -000 ---- -000 general purpose registers 10 ~ 3fh xxxx xxxx uuuu uuuu legend: u = unchanged, x = unknown, - = unimplemented, # = refer to the following table for possible values. table 2.3: rst/ to / pd status after reset or wake-up rst to pd reset was caused by 0 1 1 power-on reset 0 1 1 brown-out reset 0 u u rstb reset during normal operation 0 1 0 rstb reset during sleep 0 0 1 wdt reset during normal operation 0 0 0 wdt wake-up during sleep 1 1 0 wake-up on pin change during sleep legend: u = unchanged table 2.4: events affecting to / pd status bits event to pd power-on 1 1 wdt time-out 0 u sleep instruction 1 0 clrwdt instruction 1 1 legend: u = unchanged
chengpin CP8053 p.22/CP8053 2.7 hexadecimal convert to decimal (hcd) decimal format is another number format for CP8053. when t he content of the data memo ry has been assigned as decimal format, it is necessary to convert the results to dec imal format after the execution of alu instructions. when the decimal converting operation is processing, all of t he operand data (including the contents of the data memory (ram), accumulator (acc), immediate data, and look-up tabl e) should be in the decimal format, or the results of conversion will be incorrect. instruction daa can convert the acc data from hexadecimal to decimal format after any addition operation and restored to acc. the conversion operation is il lustrated in example 2.2. example 2.2: daa conversion movia 90h ;set immediate data = decimal format number ?90? (acc ? 90h) movar 30h ;load immediate data ?90? to data memory address 30h movia 10h ;set immediate data = decimal format number ?10? (acc ? 10h) addar 30h, 0 ;contents of the data memo ry address 30h and acc are binary-added ;the result loads to the acc (acc ? a0h, c ? 0) daa ;convert the content of acc to decimal format, and restored to acc ;the result in the acc is ?00? and the carry bit c is ?1?. this represents the ;decimal number ?100? instruction das can convert the ac c data from hexadecimal to decimal format after any subtraction operation and restored to acc. the conversion operation is illu strated in example 2.3. example 2.3: das conversion movia 10h ;set immediate data = decimal format number ?10? (acc ? 10h) movar 30h ;load immediate data ?10? to data memory address 30h movia 20h ;set immediate data = decimal format number ?20? (acc ? 20h) subar 30h, 0 ;contents of the data memory address 30h and acc are binary-subtracted ;the result loads to the acc (acc ? f0h, c ? 0) das ;convert the content of acc to decimal format, and restored to acc ;the result in the acc is ?90? and the carry bit c is ?0?. this represents the ;decimal number ? -10?
chengpin CP8053 p.23/CP8053 2.8 oscillator configurations CP8053 can be operated in four different oscillator modes. users can program two configuration bits (fosc<1:0>) to select the appropriate modes: ?3 lf: low frequency crystal oscillator ?3 hf: high frequency crystal/resonator oscillator ?3 irc: internal o r external resi stor/internal capacitor oscillator ?3 erc: external resistor/capacitor oscillator in lf, or hf modes, a crystal or ceramic resonator in conn ected to the osci and osco pins to establish oscillation. when in lf, or hf modes, the devices can have an external clock source drive the osci pin. the erc device option offers additional cost savings fo r timing insensitive applications. the rc oscillator frequency is a function of the resistor (rext) and capa citor (cext), the operating temperature, and the process parameter. the irc device option offers largest cost savings for timing insensitive applications. t hese devices offer 4 different internal rc oscillator frequency, 8mhz, 4mh z, 1mhz, and 455khz, which is selected by two configuration bits (rcm<1:0>). or user can change the oscillator frequency wi th external resistor. the irc oscillator frequency is a function of the resistor (rext, optional), the operating temperat ure, and the process parameter. figure 2.6: hf, or lf oscillator modes (crystal operation or ceramic resonator) figure 2.7: hf, or lf oscillator modes (external clock input operation) figure 2.8: erc oscillator mode (external rc oscillator) CP8053 osci osco sleep internal circuit rs x?tal c1 c2 rf CP8053 osci osco open clock from external system CP8053 osci osco rext internal circuit /2, /4 cext
chengpin CP8053 p.24/CP8053 figure 2.9: irc oscillator mode (external r, internal c oscillator) figure 2.10: irc oscillator mode (internal r, internal c oscillator) CP8053 osci osco rext internal circuit /2, /4 c CP8053 osci osco internal circuit /2, /4 c
chengpin cp 8053 p.25/CP8053 2.9 configurations word table 2.4: configurations word 0 bit name description 1, 0 fosc<1:0> oscillator selection bits = 1, 1 ? erc mode (external r & c) (default) = 1, 0 ? irc mode (external or internal r & internal c) = 0, 1 ? hf mode = 0, 0 ? lf mode 2 wdten watchdog timer enable bit = 1, wdt enabled (default) = 0, wdt disabled 3 protect code protection bit = 1, eprom code protection off (default) = 0, eprom code protection on 5, 4 lvdt<1:0> low voltage detector selection bit = 1, 1 ? disable (default) = 0, 1 ? enable, lvdt voltage = 2.0v = 0, 0 ? enable, lvdt voltage = 3.6v 7, 6 rcm<1:0> irc mode selection bits = 1, 1 ? 4mhz (default) = 1, 0 ? 8mhz = 0, 1 ? 1mhz = 0, 0 ? 455khz 9, 8 sut<1:0> wdt time period selection bits (the value must be a multiple of prescaler rate) = 1, 1 ? 18ms (default) = 1, 0 ? 4.5ms = 0, 1 ? 288ms = 0, 0 ? 72ms 10 oscin iob5/osci pin selection bit for irc mode = 1, osci pin is selected, with external r & internal c (default) = 0, iob5 pin is selected, with internal r & c 11 oscout iob4/osco pin selection bit for irc/erc mode = 1, osco pin is selected (default) = 0, iob4 pin is selected 12 rstbin iob3/rstb pin selection bit = 1, iob3 pin is selected (default) = 0, rstb pin is selected table 2.5: configurations word 1 bit name description 3 ~ 0 cal<3:0> calibration selection bits for irc mode 4 - unused 5 oscd instruction period selection bit = 1 ? four oscillator periods (default) = 0 ? two oscillator periods 7, 6 pmod<1:0> power mode selection bits = 1, 1 ? power mode 3, non-power saving (default) = 1, 0 ? power mode 2, power saving = 0, 1 ? power mode 1, power saving = 0, 0 ? power mode 0, power saving 12 ~ 8 - unused
chengpin CP8053 p.26/CP8053 table 2.6: selection of iob5/osci and iob4/osco pins mode of oscillation iob5/osci iob4/osco iob5 (oscin=0) iob4/osco se lected by oscout bit irc osci (oscin=1) iob4/osco selected by oscout bit erc osci iob4/osco selected by oscout bit hf osci osco lf osci osco
chengpin cp 8053 p.27/CP8053 3.0 instruction set mnemonic, operands description operation cycles status affected bcr r, bit clear bit in r 0 ? r 1 - bsr r, bit set bit in r 1 ? r 1 - btrsc r, bit test bit in r, skip if cle ar skip if r = 0 1/2 (1) - btrss r, bit test bit in r, skip if set skip if r = 1 1/2 (1) - nop no operation no operation 1 - clrwdt clear watchdog timer 00h ? wdt, 00h ? wdt prescaler 1 to , pd option load option register acc ? option 1 - sleep go into power-down mode 00h ? wdt, 00h ? wdt prescaler 1 to , pd daa adjust acc?s data format from hex to dec after any addition operation acc(hex) ? acc(dec) 1 c das adjust acc?s data format from hex to dec after any subtraction operation acc(hex) ? acc(dec) 1 - int s/w interrupt pc + 1 ? top of stack, 002h ? pc 2 - return return from subroutine top of stack ? pc 2 - retfie return from interrupt, set gie bit top of stack ? pc, 1 ? gie 2 - clra clear acc 00h ? acc 1 z iost r load iost register acc ? iost register 1 - clrr r clear r 00h ? r 1 z movar r move acc to r acc ? r 1 - movr r, d move r r ? dest 1 z decr r, d decrement r r - 1 ? dest 1 z decrsz r, d decrement r, skip if 0 r - 1 ? dest, skip if result = 0 1/2 (1) - incr r, d increment r r + 1 ? dest 1 z incrsz r, d increment r, skip if 0 r + 1 ? dest, skip if result = 0 1/2 (1) - addar r, d add acc and r r + acc ? dest 1 c, dc, z subar r, d subtract acc from r r - acc ? dest 1 c, dc, z adcar r, d add acc and r with carry r + acc + c ? dest 1 c, dc, z sbcar r, d subtract acc from r with carry r + acc + c ? dest 1 c, dc, z andar r, d and acc with r acc and r ? dest 1 z iorar r, d inclusive or acc with r acc or r ? dest 1 z xorar r, d exclusive or acc with r r xor acc ? dest 1 z comr r, d complement r r ? dest 1 z rlr r, d rotate left f through carry r<7> ? c, r<6:0> ? dest<7:1>, c ? dest<0> 1 c
chengpin CP8053 p.28/CP8053 rrr r, d rotate right f through carry c ? dest<7>, r<7:1> ? dest<6:0>, r<0> ? c 1 c swapr r, d swap r r<3:0> ? dest<7:4>, r<7:4> ? dest<3:0> 1 - movia i move immediate to acc i ? acc 1 - addia i add acc and immediate i + acc ? acc 1 c, dc, z subia i subtract acc from immediate i - acc ? acc 1 c, dc, z andia i and immediate with acc acc and i ? acc 1 z ioria i or immediate with acc acc or i ? acc 1 z xoria i exclusive or immediate to acc acc xor i ? acc 1 z retia i return, place immediate in acc i ? acc, top of stack ? pc 2 - call i call subroutine pc + 1 ? top of stack, i ? pc 2 - goto i unconditional branch i ? pc 2 - note: 1. 2 cycles for skip, else 1 cycle 2. bit : bit address within an 8-bit register r r : register address (00h to 3fh) i : immediate data acc : accumulator d : destination select; =0 (store result in acc) =1 (store result in file register r) dest : destination pc : program counter pchbuf : high byte buffer of program counter wdt : watchdog timer counter gie : global interrupt enable bit to : time-out bit pd : power-down bit c : carry bit dc : digital carry bit z : zero bit
chengpin CP8053 p.29/CP8053 adcar add acc and r with carry syntax: adcar r, d operands: 0
chengpin cp 8053 p.30/CP8053 bcr clear bit in r syntax: bcf r, b operands: 0 d r d 63 0 d b d 7 operation: 0 ? r status affected: none description: clear bit ?b? in register ?r?. cycles: 1 bsr set bit in r syntax: bsr r, b operands: 0 d r d 63 0 d b d 7 operation: 1 ? r status affected: none description: set bit ?b? in register ?r?. cycles: 1 btrsc test bit in r, skip if clear syntax: btrsc r, b operands: 0 d r d 63 0 d b d 7 operation: skip if r = 0 status affected: none description: if bit ?b? in register ?r? is 0 then the next instruction is skipped. if bit ?b? is 0 then next instruction fetched duri ng the current instruction execution is discarded, and a nop is executed instead making this a 2-cycle instruction.. cycles: 1(2) btrss test bit in r, skip if set syntax: btrss r, b operands: 0 d r d 63 0 d b d 7 operation: skip if r = 1 status affected: none description: if bit ?b? in register ?r? is ?1? then the next instruction is skipped. if bit ?b? is ?1?, then the next instruction fetch ed during the current inst ruction execution, is discarded and a nop is executed instead, making this a 2-cycle instruction. cycles: 1(2) call subroutine call syntax: call i operands: 0 d i d 1023 operation: pc +1 ? top of stack; i ? pc status affected: none description: subroutine call. first, return address (p c+1) is pushed onto the stack. the 10-bit immediate address is loaded into pc bits <9:0>. call is a two-cycle instruction. cycles: 2
chengpin cp 8053 p.31/CP8053 clra clear acc syntax: clra operands: none operation: 00h ? acc; 1 ? z status affected: z description: the acc register is cleared. zero bit (z) is set. cycles: 1 clrr clear r syntax: clrr r operands: 0 d r d 63 operation: 00h ? r; 1 ? z status affected: z description: the contents of register ?r? are cleared and the z bit is set. cycles: 1 clrwdt clear watchdog timer syntax: clrwdt operands: none operation: 00h ? wdt; 00h ? wdt prescaler (if assigned); 1 ? to ; 1 ? pd status affected: to , pd description: the clrwdt instruction resets the wdt. it also resets the prescaler, if the prescaler is assigned to the wdt and not timer0. status bits to and pd are set. cycles: 1 comr complement r syntax: comr r, d operands: 0 d r d 63 d ? [0,1] operation: r ? dest status affected: z description: the contents of register ?r? are complemented. if ?d? is 0 the result is stored in the acc register. if ?d? is 1 the result is stored back in register ?r?. cycles: 1 daa adjust acc?s data format from hex to dec syntax: daa operands: none operation: acc(hex) ? acc(dec) status affected: c description: convert the acc data from hexadecimal to decimal format after any addition operation and restored to acc. cycles: 1
chengpin CP8053 p.32/CP8053 das adjust acc?s data format from hex to dec syntax: das operands: none operation: acc(hex) ? acc(dec) status affected: none description: convert the acc data from hexadecimal to decimal format after any subtraction operation and restored to acc. cycles: 1 decr decrement r syntax: decr r, d operands: 0 d r d 63 d ? [0,1] operation: r - 1 ? dest status affected: z description: decrement register ?r?. if ?d ? is 0 the result is stor ed in the acc register. if ?d? is 1 the result is stored back in register ?r?. cycles: 1 decrsz decrement r, skip if 0 syntax: decrsz r, d operands: 0 d r d 63 d ? [0,1] operation: r - 1 ? dest; skip if result =0 status affected: none description: the contents of register ?r? are decremented. if ?d? is 0 the result is placed in the acc register. if ?d? is 1 the result is placed back in register ?r?. if the result is 0, the next in struction, which is already fetched, is discarded and a nop is executed instead making it a two-cycle instruction. cycles: 1(2) goto unconditional branch syntax: goto i operands: 0 d i d 1023 operation: i ? pc status affected: none description: goto is an unconditional branch. the 10-bit immediate value is loaded into pc bits <9:0>. goto is a two-cycle instruction. cycles: 2 incr increment r syntax: incr r, d operands: 0 d r d 63 d ? [0,1] operation: r + 1 ? dest status affected: z description: the contents of register ?r ? are incremented. if ?d? is 0 the re sult is placed in the acc register. if ?d? is 1 the result is placed back in register ?r?. cycles: 1
chengpin CP8053 p.33/CP8053 incrsz increment r, skip if 0 syntax: incrsz r, d operands: 0
chengpin CP8053 p.34/CP8053 movar move acc to r syntax: movar r operands: 0 d r d 63 operation: acc ? r status affected: none description: move data from the acc register to register ?r?. cycles: 1 movia move immediate to acc syntax: movia i operands: 0 d i d 255 operation: i ? acc status affected: none description: the 8-bit immediate ?i? is loaded into the acc register. the don?t cares will assemble as 0s. cycles: 1 movr move r syntax: movr r, d operands: 0 d r d 63 d ? [0,1] operation: r ? dest status affected: z description: the contents of register ?r? is moved to destination ?d?. if ?d? is 0, destination is the acc register. if ?d? is 1, the destination is file register ?r?. ?d? is 1 is useful to test a file register since status flag z is affected. cycles: 1 nop no operation syntax: nop operands: none operation: no operation status affected: none description: no operation. cycles: 1 option load option register syntax: option operands: none operation: acc ? option status affected: none description: the content of the acc register is loaded into the option register. cycles: 1 retfie return from in terrupt, set ?gie? bit syntax: retfie operands: none operation: top of stack ? pc status affected: none description: the program counter is lo aded from the top of t he stack (the return address). the ?gie? bit is set to 1. this is a two-cycle instruction. cycles: 2
chengpin CP8053 p.35/CP8053 retia return with immediate in acc syntax: retia i operands: 0
chengpin cp 8053 p.36/CP8053 sleep enter sleep mode syntax: sleep operands: none operation: 00h ? wdt; 00h ? wdt prescaler; 1 ? to ; 0 ? pd status affected: to , pd description: time-out status bit ( to ) is set. the power-down status bit ( pd ) is cleared. the wdt and its prescaler are cleared. the processor is put into sleep mode. cycles: 1 sbcar subtract acc from r with carry syntax: sbcar r, d operands: 0 d r d 63 d ? [0,1] operation: r + acc + c ? dest status affected: c, dc, z description: add the 2?s complement met hod of the acc register fr om register ?r? with carry. if ?d? is 0 the result is stored in the acc register. if ?d? is 1 the result is stored back in register ?r?. cycles: 1 subar subtract acc from r syntax: subar r, d operands: 0 d r d 63 d ? [0,1] operation: r - acc ? dest status affected: c, dc, z description: subtract (2?s complement method) the acc register from regist er ?r?. if ?d? is 0 the result is stored in the acc register. if ?d? is 1 t he result is stored back in register ?r?. cycles: 1 subia subtract acc from immediate syntax: subar r, d operands: 0 d i d 255 operation: i - acc ? acc status affected: c, dc, z description: subtract (2?s complement method) the acc register from the 8-bit immediate ?i?. the result is placed in the acc register. cycles: 1 swapr swap nibbles in r syntax: swapr r, d operands: 0 d r d 63 d ? [0,1] operation: r<3:0> ? dest<7:4>; r<7:4> ? dest<3:0> status affected: none description: the upper and lower nibbles of register ?r? are exchanged. if ?d? is 0 the result is placed in acc register. if ?d? is 1 the resu lt in placed in register ?r?. cycles: 1
chengpin CP8053 p.37/CP8053 xorar exclusive or acc with r syntax: xorar r, d operands: 0 d r d 63 d ? [0,1] operation: acc xor r ? dest status affected: z description: exclusive or the contents of the acc register with register ?r?. if ?d? is 0 the result is stored in the acc register. if ?d? is 1 the re sult is stored back in register ?r?. cycles: 1 xoria exclusive or immediate with acc syntax: xoria i operands: 0 d i d 255 operation: acc xor i ? acc status affected: z description: the contents of the acc r egister are xor?ed with the 8-bit imm ediate ?i?. the result is placed in the acc register. cycles: 1
chengpin CP8053 p.38/CP8053 2.0 absolute maximum ratings ambient operating temperature 0 :33??: store temperature -65 :33???: dc supply voltage (vdd) 0v to +6.0v input voltage with respect to ground (vss) -0.3v to (vdd + 0.3)v 3.0 operating conditions dc supply voltage +2.3v to +5.5v operating temperature 0 :33??:
chengpin cp 8053 p.39/CP8053 4.0 electrical characteristics 6.1 electrical characteristics of CP8053e under operating conditions, at four clock in struction cycles and wdt & lvdt are disabled sym description conditions min. typ. max. unit hf mode, vdd=5v 1 20 f hf x?tal oscillation range hf mode, vdd=3v 1 15 mhz lf mode, vdd=5v 32 4000 f lf x?tal oscillation range lf mode, vdd=3v 32 1000 khz erc mode, vdd=5v dc 15 f erc rc oscillation range erc mode, vdd=3v dc 7 mhz irc mode, external r, vdd=5v dc 15 irc mode, external r, vdd=3v dc 7 irc mode, internal r, vdd=5v 0.455 8 f irc rc oscillation range irc mode, internal r, vdd=3v 0.455 8 mhz i/o ports, vdd=5v 2.0 rstb, t0cki pins, vdd=5v 2.0 i/o ports, vdd=3v 1.5 v ih input high voltage rstb, t0cki pins, vdd=3v 1.5 v i/o ports, vdd=5v 1.0 rstb, t0cki pins, vdd=5v 1.0 i/o ports, vdd=3v 0.6 v il input low voltage rstb, t0cki pins, vdd=3v 0.6 v v oh output high voltage i oh =-5.4ma, vdd=5v 3.6 v v ol output low voltage i ol =8.7ma, vdd=5v 0.6 v i ph pull-high current input pin at vss, vdd=5v -45 ua i pd pull-down current input pin at vdd, vdd=5v 35 ua vdd=5v 9 12 i wdt wdt current vdd=3v 2 4 ua vdd=3v 20.4 vdd=4v 17.9 t wdt wdt period vdd=5v 16.2 ms vdd=5v lvdt = 3.6v 30 40 vdd=5v lvdt = 2v 23 30 i lvdt lvdt current vdd=3v lvdt = 2v 6.8 8.0 ua sleep mode, vdd=5v, wdt enable 20 sleep mode, vdd=5v, wdt disable 3 sleep mode, vdd=3v, wdt enable 2.5 i sb power down current sleep mode, vdd=3v, wdt disable 1.1 ua hf mode, vdd=5v, 4 clock instruction 20mhz 2.04 15mhz 1.68 10mhz 1.28 4mhz 0.78 i dd operating current 2mhz 0.62 ma
chengpin CP8053 p.40/CP8053 hf mode, vdd=3v, 4 clock instruction 20mhz 0.92 15mhz 0.72 10mhz 0.54 4mhz 0.30 i dd operating current 2mhz 0.19 ma hf mode, vdd=5v, 2 clock instruction 20mhz 2.94 15mhz 2.34 10mhz 1.74 4mhz 0.96 i dd operating current 2mhz 0.68 ma hf mode, vdd=3v, 2 clock instruction 20mhz 1.38 15mhz 1.07 10mhz 0.77 4mhz 0.38 i dd operating current 2mhz 0.24 ma lf mode, vdd=5v, 4 clock instruction 2mhz 290 1mhz 208 500khz 167 100khz 118 i dd operating current 32khz 101 ua lf mode, vdd=3v, 4 clock instruction 2mhz 105 1mhz 73 500khz 54 100khz 33 i dd operating current 32khz 26 ua lf mode, vdd=5v, 2 clock instruction 2mhz 371 1mhz 269 500khz 194 100khz 130 i dd operating current 32khz 108 ua lf mode, vdd=3v, 2 clock instruction 2mhz 158 1mhz 100 500khz 67 100khz 38 i dd operating current 32khz 29 ua erc mode, vdd=5v, 4 clock instruction i dd operating current c=3p r=1kohm f=14.96mhz 4.572 ma
chengpin CP8053 p.41/CP8053 r=3.3kohm f=11.06mhz 1.845 r=10kohm f=5.80mhz 0.761 r=100kohm f=808khz 0.170 r=300kohm f=276khz 0.119 r=1kohm f=11.7mhz 4.226 r=3.3kohm f=6.35mhz 1.519 r=10kohm f=2.73mhz 0.613 r=100kohm f=320khz 0.147 c=20p r=300kohm f=108khz 0.109 r=1kohm f=5.23mhz 3.429 r=3.3kohm f=2.05mhz 1.163 r=10kohm f=748khz 0.454 r=100kohm f=80khz 0.126 c=100p r=300kohm f=26.4khz 0.100 r=1kohm f=2.5mhz 3.024 r=3.3kohm f=900khz 1.021 r=10kohm f=316khz 0.403 r=100kohm f=32khz 0.119 c=300p r=300kohm f=10.67khz 0.098 erc mode, vdd=3v, 4 clock instruction r=1kohm f=8.29mhz 2.280 r=3.3kohm f=7.2mhz 0.913 r=10kohm f=4.58mhz 0.396 r=100kohm f=900khz 0.071 c=3p r=300kohm f=316khz 0.040 r=1kohm f=7mhz 2.214 r=3.3kohm f=5.1mhz 0.837 r=10kohm f=2.71mhz 0.327 r=100kohm f=374khz 0.058 c=20p r=300kohm f=128khz 0.035 r=1kohm f=4.14mhz 2.060 r=3.3kohm f=2.11mhz 0.688 r=10kohm f=848khz 0.253 r=100kohm f=96khz 0.047 c=100p r=300kohm f=32khz 0.030 r=1kohm f=2.36mhz 1.890 r=3.3kohm f=972khz 0.630 r=10kohm f=360khz 0.226 r=100kohm f=38khz 0.043 i dd operating current c=300p r=300kohm f=12.71khz 0.028 ma erc mode, vdd=5v, 2 clock instruction r=1kohm f=15.16mhz 5.435 r=3.3kohm f=11.27mhz 2.358 r=10kohm f=5.77mhz 986 r=100kohm f=826khz 0.183 c=3p r=300kohm f=274khz 0.108 i dd operating current c=20p r=1kohm f=11.56mhz 4.835 ma
chengpin cp 8053 p.42/CP8053 r=3.3kohm f=6.12mhz 1.808 r=10kohm f=2.72mhz 0.701 r=100kohm f=308khz 0.138 r=300kohm f=105khz 0.092 r=1kohm f=5.32mhz 3.680 r=3.3kohm f=1.99mhz 1.234 r=10kohm f=722khz 0.479 r=100kohm f=77khz 0.110 c=100p r=300kohm f=25.0khz 0.081 r=1kohm f=2.52mhz 3.107 r=3.3kohm f=892khz 1.057 r=10kohm f=312khz 0.398 r=100kohm f=32khz 0.102 c=300p r=300kohm f=11khz 0.077 erc mode, vdd=3v, 2 clock instruction r=1kohm f=8.306mhz 2.552 r=3.3kohm f=7.29mhz 1.130 r=10kohm f=4.81mhz 0.518 r=100kohm f=904khz 0.084 c=3p r=300kohm f=338khz 0.039 r=1kohm f=7.08mhz 2.445 r=3.3kohm f=5.07mhz 0.986 r=10kohm f=2.68mhz 0.393 r=100kohm f=362khz 0.061 c=20p r=300kohm f=123khz 0.031 r=1kohm f=4.11mhz 2.197 r=3.3kohm f=2.03mhz 0.745 r=10kohm f=810khz 0.270 r=100kohm f=91khz 0.043 c=100p r=300kohm f=30khz 0.025 r=1kohm f=2.37mhz 1.953 r=3.3kohm f=964khz 0.648 r=10kohm f=354khz 0.231 r=100kohm f=38khz 0.038 i dd operating current c=300p r=300kohm f=13khz 0.022 ma irc mode, external r, vdd=5v, 4 clock instruction r=1kohm f=15.16mhz r=3.3kohm f=11.27mhz r=10kohm f=5.77mhz r=100kohm f=826khz i dd operating current r=300kohm f=274khz ma irc mode, external r, vdd=3v, 4 clock instruction i dd operating current r=1kohm f=15.16mhz ma
chengpin cp 8053 p.43/CP8053 r=3.3kohm f=11.27mhz r=10kohm f=5.77mhz r=100kohm f=826khz r=300kohm f=274khz irc mode, external r,vdd=5v, 2 clock instruction r=1kohm f=15.16mhz r=3.3kohm f=11.27mhz r=10kohm f=5.77mhz r=100kohm f=826khz i dd operating current r=300kohm f=274khz ma irc mode, external r,vdd=3v, 2 clock instruction r=1kohm f=15.16mhz r=3.3kohm f=11.27mhz r=10kohm f=5.77mhz r=100kohm f=826khz i dd operating current r=300kohm f=274khz ma irc mode, internal r, vdd=5v, 4 clock instruction f=8mhz f=4mhz f=1mhz i dd operating current f=455khz ma irc mode, internal r, vdd=3v, 4 clock instruction f=8mhz f=4mhz f=1mhz i dd operating current f=455khz ma irc mode, internal r,vdd=5v, 2 clock instruction f=8mhz f=4mhz f=1mhz i dd operating current f=455khz ma irc mode, internal r,vdd=3v, 2 clock instruction f=8mhz f=4mhz f=1mhz i dd operating current f=455khz ma 6.2 electrical characteristics of CP8053 to be defined
chengpin CP8053 p.44/CP8053 5.0 package dimension 7.1 14-pin pdip 300mil e1 ? d ?? ? e o e b 0.060typ. l 0.100typ. 0.018typ. dimension in inches symbols min nom max a - - 0.210 a1 0.015 - - a2 0.125 0.130 0.135 d 0.735 0.750 0.775 e 0.300 bsc. e1 0.245 0.250 0.255 l 0.115 0.130 0.150 eb 0.335 0.355 0.375
chengpin cp 8053 p.45/CP8053 7.2 14-pin sop 150mil ? ? ? ? o ?? ? h ? ? ?? e ? ? ? ? ? d a a1 0.004max ? ? ??3???? ????3???? ????33? o dimension in inches symbols min nom max a 0.058 0.064 0.068 a1 0.004 - 0.010 b 0.013 0.016 0.020 c 0.0075 0.008 0.0098 d 0.336 0.341 0.344 e 0.150 0.154 0.157 e - 0.050 - h 0.228 0.236 0.244 l 0.015 0.025 0.050 o 0 o - 8 o
chengpin CP8053 p.46/CP8053 8.0 ordering information otp type mcu package type pin count package size CP8053p pdip 14 300 mil CP8053s sop 14 150 mil

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